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FWD>RE>Serial D-1 Jitter

Mail*Link(r) SMTP               FWD>RE>Serial D-1 Jitter

Thanks for the hints.  Most of our jitter problems are from Rank and look to
be related to the PLL on the 934 cards.  This is in both the MK3 Digi-4's and
the URSA 4:2:2 machines.  Jitter after serialization is measured around 1.40
ns on the AAVS Digital Signal Analyser.  By letting the machines free run
(remove the reference sync feed to the Rank and it free runs on internal sync
gen) the jitter goes way down to around 0.30 ns. So now what?  Redesign the
PLL gen lock circuit?

Craig, did you measure jitter before and after doing the Rank change note
mods? Steve Prager tells me he may start work on a reclocking and de-jittering
DA for the jittery Rank outputs, like a TBC for D-1 jitter.  Does anyone out
there make such a beast at a reasonable price?  I would think it would be
easiest to fix it at the source, the Rank PLL circuit.  Other devices of a
similar design vintage have similar problems such as the Abekas A-60.  We will
be installing URSA 4:4:4 upgrade kits soon on our two 4:2:2 URSAs so I will be
able to report back to the group on whether or not the jitter is improved.
Dave Corbitt


Craig Nichols wrote--->
>   There must be a better way (like maybe better phase lock loop design ;-)
>   anyone aware of reclocking DAs that really do eliminate jitter?
>   On the Rank output side of things, I just did Rank change note 33102 that
>   provides a more direct route for 27 Mhz between the 1030 and 934 board,
>   it has helped clean up the eye pattern a little in Pal, but it is far from
>   The other changes they are suggesting is hand picking some of the ICs. I
>   have not tried this somewhat "voodotronic" approach yet, but Rank has a
>   of "the usual suspects".
>   I know that Mark IIIs and Ursas suffer from about the same jitter.  The
>   uses a little different sync generator scheme to generate the clock.  Is
>   any more stable?