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Re: Reclocking Serial DA

--- Forwarded mail from steveb at pandora-int.com (Steve Brett)

>Its been my experience that "reclocking" DAs just reshape the jitter, in
>essence just passing along a cleaned up version with nearly equal jitter.
>There must be a better way (like maybe better phase lock loop design ;-) Is
>anyone aware of reclocking DAs that really do eliminate jitter?

We [PANDORA] have a reclocking serial DA that should meet this requirement.
I built this as part of a project we have that requires 400MBs data  rates
and so spec for clock jitter is rather more stringent than usual  !!!    I
have checked jitter performance at 270MHz and this shows that with in input
signal exhibiting a jitter of around 1nS peak to peak output jitter is
reduced to less than 100pS.
We did not really intend to sell this board as a stand alone product but if
anyone is interested please let me know...

Incidentally we have found different batches of the Sony 1601 Serialiser
chip [which is fairly common] to exhibit wildly different performance in
respect to PLL stability. They are also fairly fussy about temperature and
quality of power supply.
In general the performance of most plug-top serialisers can be improved by
using a good quality regulated supply and cutting the length of the power
cable to an absolute minimum. I have also found in a couple of cases that
re-routing the Supply Ground wire to a point in the circuit very close to
the PLL loop filter can dramatically improve performance.

Newer parts from Gennum Corporation are in general much better behaved but
unfortunately  they are not at all compatible with the Sony type.

--- End of forwarded message from steveb at pandora-int.com (Steve Brett)